The present invention relates to a circuit, and in particular a circuit for calibrating an output driver current.
In high performance output driver circuits, the output current should be maintained or calibrated to a desirable value. There are a number of ways of calibrating an output current.
First, a desired output current may be obtained through closed-loop continuous calibration. If a binary weighted current control digital-to-analog converter (xe2x80x9cDACxe2x80x9d) is used, closed-loop continuous time calibration can introduce unacceptable noise into the output current.
Second, a desired output current may be obtained through open-loop discrete time calibration.
Third, a thermometer-coded DAC can be used, but this may introduce large capacitance at a pin. In high-speed link design, minimizing pin capacitance enables improved performance.
Once an appropriate output current is calibrated, distributing information regarding the output current to other output drivers or pins is desirable. Generally, information regarding the calibrated output current can be transferred to other output drivers by a current distribution network using either a current passing or a voltage passing technique.
FIG. 2 illustrates a current distribution network 200 using a current passing technique. An N-bit DAC generates a current to transistors 213-210 in response to n bit values. An N-bit DAC includes N transistors. A biasing current then may be generated to output driver 230. Output driver 230 includes terminal resistors 202 and 203. A biasing current is applied to transistor 209 and transistor 206. Transistors 204 and 205 are coupled to transistor 206. A disadvantage of network 200 is that a calibration time will be too lengthy for a typical current mirror current. Current mirrors formed by transistors 213-210 and 209 and 206 have large resistance capacitance (xe2x80x9cRCxe2x80x9d) time constants for a typical current. In high performance applications, a lengthy calibration time will degrade apparatus or system efficiency.
FIG. 3 illustrates a current distribution network 300 using a voltage passing technique. Output drivers 301 and 302 pass voltage over line 340 and voltage supply VSS. Output driver 301 includes terminal resistors 306 and 303 coupled to transistors 304 and 305, respectively. Gates of transistors 310-312 are coupled to line 340 and drains are coupled to transistors 304 and 305. Drains of transistors 313-315 are coupled to the sources of transistors 310-312, respectively, and sources of transistors 313-315 are coupled to voltage source VSS. Output driver 302, similar to output driver 301 includes terminal resistors 330 and 331 coupled to transistors 332 and 333. Gates of transistors 320-322 are coupled to line 340 and sources of transistors 320-322 are coupled to transistors 323-325. A disadvantage of network 300 is that there will be pin-to-pin current variations due to current/resistance (xe2x80x9cIRxe2x80x9d) drop on voltage source VSS. For example, a voltage drop between a drain of transistor 310 and a source of transistor 313 in output driver 301 will not typically be precisely the same as the voltage drop between a drain of transistor 320 and a source of transistor 323 in output driver 302. As voltage supplies continue to scale down, the transistor gate override will be decreased making this disadvantage worse. Pin-to-pin current variations due to IR drop will be undesirably large for a typical voltage source Vss bus width.
There is also a common disadvantage of networks 200 and 300 shown in FIGS. 2 and 3, respectively. An output driver LSB current is varied greatly due to process/temperature/power supply variations. For example, a current generated by transistors 312 and 315 is considered a LSB current for output driver 301. If a desired output current is I, in a slow process, high temperature and low supply condition, a LSB current is (I/2N) where N is the number of bits in an N-bit DAC. In a fast process, low temperature and high supply voltage, the LSB current could be several times larger than (I/2N). This is very undesirable when high accuracy current control is needed to improve system margin.
Therefore, it is desirable to provide a circuit, apparatus and a method for efficiently and accurately calibrating an output driver, and in particular efficiently and accurately calibrating output driver current in a high performance apparatus.
A circuit, apparatus and method for efficiently and accurately calibrating an output driver are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (xe2x80x9cDACxe2x80x9d) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current.
According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs.
According to an embodiment of the present invention, the binary weighted value of the second DAC is obtained in response to a calibration signal generated by a controller.
According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N.
According to an embodiment of the present invention, the second DAC is a current source of an output driver.
According to another embodiment of the present invention, the second DAC is coupled to a pin.
According to still another embodiment of the present invention, the first transistor is a p-type transistor.
According to an embodiment of the present invention, the binary weighted values are stored in a register.
According to an embodiment of the present invention, the circuit is in a memory device.
According to an embodiment of the present invention, a second transistor is coupled to the first DAC and generates a second biasing current responsive to the first current. A third DAC is coupled to the second transistor and generates a second control current responsive to the second biasing current.
According to an embodiment of the present invention, a current distribution circuit in a memory device comprises a first M-bit DAC generating a first current. A first transistor is coupled to the first M-bit DAC and generates a first biasing current responsive to the first current. A second N-bit DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. A second transistor is coupled to the first M-bit DAC and generates a second biasing current responsive to the first current. A third N-bit DAC is coupled to the second transistor and generates a second control current responsive to the second biasing current.
According to another embodiment of the present invention, the memory device is a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) device or a Rambus Dynamic Random Access Memory (xe2x80x9cRDRAMxe2x80x9d) device.
According to an embodiment of the present invention, the first and second transistors are p-type transistors.
According to an embodiment of the present invention, the second DAC is coupled to a first pin and the third DAC is coupled to a second pin.
According to an embodiment of the present invention, an apparatus for calibrating an output driver comprises a controller generating a calibration signal. A device is coupled to the controller and generates an output current in response to the calibration signal. The device includes a circuit having a first M-bit DAC to generate a first current. A first transistor is coupled to the first M-bit DAC and generates a first biasing current responsive to the first current. A second N-bit DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. A second transistor is coupled to the first M-bit DAC and generates a second biasing current responsive to the first current. A third N-bit DAC is coupled to the second transistor and generates a second control current responsive to the second biasing current.
According to an embodiment of the present invention, a method for calibrating an output driver is provided. M values are provided to an M-bit DAC to generate a first current value. A first biasing current, in response to the first current value, is provided to an N-bit DAC coupled to the output driver. The m most significant bit values of the N-bit DAC is obtained. The m most significant bits are applied to the M-bit DAC to generate a second current value. A second biasing current is provided, in response to the second current, to the N-bit DAC. A control current is obtained for the output driver in response to the second biasing current.
These and other embodiments of the present invention, as well as other aspects and advantages are described in more detail in conjunction with the figures, the detailed description, and the claims that follow.